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| A8351601 Series Bar Code Reader Document Title Bar Code Reader Revision History Rev. No. 0.0 0.1 History Initial issue Change document title from "Bar Code Reader" to "8 Bit Microcontroller" Error correction: (1) Delete single-step operation description (2) Delete "the only exit from power down is a hardware reset" on page 32 Issue Date June 5, 2000 June 22, 2000 Remark Preliminary 0.2 0.3 Modify 44L QFP package outline drawing and dimensions Modify PWM function (1) Add PWM3 delay control bits D0, D1 and D2 (2) Add PWM4 output control bit PWM1.7 November 15, 2000 January 17, 2001 0.4 0.5 0.6 1.0 Error correction: Delete Functional Description Change document title from "8 Bit Microcontroller" to "Bar Code Reader" Modify AC, DC Electrical Characteristics: Add 3V 10% condition SFR Map address has some typewriting errors Modify DC and AC Electrical Characteristics Final version release June 6, 2001 October 16, 2001 February 19, 2002 July 12, 2002 Final (July, 2002, Version 1.0) AMIC Technology, Inc. A8351601 Series Bar Code Reader Features n 80C32 CPU core n Build in 64K byte OTP ROM n Build in 8K byte external SRAM (0000H - 1FFFH), can be disable by SFR n Fully pin compatible with standard 8051 family interface n Instruction set compatible with 8051 family n Option frequency 4.5V-5.5V:0-40MHz, 2.7V-3.3V:0-16MHz n Power saving operation: Idle is compatible with 8051 family Power down can be wake up by external interrupt n Port0~Port3 with internal pull-up n Four channel PWM output for PLCC & QFP package n Capture function with T2EX reversed mode n Operation temperature: -10C~70C n ESD > 3KV n Double frequency selected by SFR General Description The AMIC A8351601 is a high-performance 8-bit microcontroller. It is compatible with the industry standard 80C52 microcontroller series. The A8351601 contains a on chip 256 byte RAM, 64K byte OTP ROM, 8K byte external data SRAM, four 8-bit bidirectional parallel ports, three 16-bit timer/counters, a serial port and six interrupt sources with two priority levels. The A8351601 has supports 64KB external data memory. (July, 2002, Version 1.0) 1 AMIC Technology, Inc. A8351601 Series Pin Configurations n P-DIP n PLCC P1.1,T2EX P0.0,AD0 P0.1,AD1 42 P0.2,AD2 41 T2,P1.0 T2EX,P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD,P3.0 TXD,P3.1 INT0,P3.2 INT1,P3.3 T0,P3.4 T1,P3.5 WR,P3.6 RD,P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0,AD0 P0.1,AD1 P0.2,AD2 P0.3,AD3 P0.4,AD4 P0.5,AD5 P0.6,AD6 P0.7,AD7 EA ALE PSEN P2.7,A15 P2.6,A14 P2.5,A13 P2.4,A12 P2.3,A11 P2.2,A10 P2.1,A9 P2.0,A8 6 5 4 3 2 1 44 43 40 39 38 37 36 35 34 33 32 31 30 29 P1.5 P1.6 P1.7 RST RXD,P3.0 PWM2 TXD,P3.1 INT0, P3.2 INT1,P3.3 T0,P3.4 T1,P3.5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P0.3,AD3 P1.0,T2 PWM1 VCC P1.4 P1.3 P1.2 P0.4,AD4 P0.5,AD5 P0.6,AD6 P0.7,AD7 EA PWM4 ALE PSEN P2.7,A15 P2.6,A14 P2.5,A13 RD,P3.7 XTAL2 XTAL1 GND PWM3 P2.2,A10 n QFP P1.1,T2EX P0.0,AD0 P0.1,AD1 P0.2,AD2 44 43 42 41 40 39 38 37 36 35 P1.5 P1.6 P1.7 RST RXD,P3.0 PWM2 TXD,P3.1 INT0, P3.2 INT1,P3.3 T0,P3.4 T1,P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 P0.3,AD3 P1.0,T2 PWM1 VCC P1.4 P1.3 P1.2 33 32 31 30 29 28 27 26 25 24 23 P0.4,AD4 P0.5,AD5 P0.6,AD6 P0.7,AD7 EA PWM4 ALE PSEN P2.7,A15 P2.6,A14 P2.5,A13 WR,P3.6 RD,P3.7 XTAL2 XTAL1 GND PWM3 P2.2,A10 P2.3,A11 P2.4,A12 P2.0,A8 P2.1,A9 (July, 2002, Version 1.0) 2 AMIC Technology, Inc. P2.3,A11 P2.4,A12 WR,P3.6 P2.0,A8 P2.1,A9 A8351601 A8351601L A8351601F A8351601 Series Block Diagram PSEN ALE EA RST XTAL1 XTAL2 P0.0-P0.7 (AD0-AD7) P2.0-P2.7 A8-A15 SFR 64KB OTP 8KB SRAM TIMING AND CONTROL OSCILLATOR PORT 0 ADDRESS PORT 2 ADDRESS CPU CORE TIMER 2 INTERRUPT SERIAL PORT TIMER 0.1 PWM 256B RAM PORT 1 PORT 3 P1.0-P1.7 P3.0-P3.7 (July, 2002, Version 1.0) 3 AMIC Technology, Inc. A8351601 Series Pin Description Pin No. Symbol P-DIP ALE 30 PLCC 33 QFP 27 O Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. External Access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory. Port 0: Port 0 is an 8-bit bidirectional I/O port with internal pullups. Port 0 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). The Port 1 output buffers can sink/source four TTL inputs. T2 (P1.0): Timer/Counter 2 external count input. T2EX (P1.1): Timer/Counter 2 trigger input. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that used 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order bits and some control signals during ROM verification. I/O Description EA 31 35 29 I P0.0-P0.7 32-39 36-43 30-37 I/O P1.0-P1.7 1-8 2-9 40-44 I/O 1 2 P2.0-P2.7 21-28 2 3 24-31 40 41 18-25 I I I/O (July, 2002, Version 1.0) 4 AMIC Technology, Inc. A8351601 Series Pin Description (continued) Pin No. Symbol P-DIP P3.0-P3.7 10-17 PLCC 11,13-19 QFP 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: IIL). Port 3 also serves the special features of the A8351601, as listed below: RxD (P3.0): Serial input port. TxD (P3.1): Serial output port. I/O Description 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 32 5 7 8 9 10 11 12 13 26 I O I I I I O O O INT0 (P3.2): External interrupt 0. INT1 (P3.3): External interrupt 1. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle except that two PSEN actives are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. Pulse width modulation 1 output. Pulse width modulation 2 output. (D2, D1, D0) controlled the delay time of PWM3 from 4 CLK to 11 CLK after PWM1 change. PWM1.7: 1 is PWM3/4096, 75% duty (3072 PWM3 cycle high, 1024 PWM3 cycle low) PWM1.7: 0 is PWM3/1024, 67% duty (2048 PWM3 cycle high, 1024 PWM3 cycle low) PSEN 29 RST PWM1 PWM2 PWM3 PWM4 9 10 1 12 23 34 4 39 6 17 28 I O O O O XTAL1 XTAL2 GND VCC 19 18 20 40 21 20 22 44 15 14 16 38 I O I I Crystal 1: Input to the inverting oscillator and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator. Ground: 0V reference. Power Supply: This is the power supply voltage for operation. (July, 2002, Version 1.0) 5 AMIC Technology, Inc. A8351601 Series Operating Description The detail description of the A8351601 included in this description are: n Memory Map and Registers n Timer/Counters n Serial Interface n Interrupt System n Other Information The lower 128 bytes of RAM can be divided into three segments as listed below. 1. Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1byte registers R0-R7. Reset initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank. 2. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction. Memory Map and Registers Memory The A8351601 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes. The A8351601 has 256 bytes of on-chip RAM, plus numbers of special function registers. The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. The upper 128 bytes can be accessed by indirect addressing only. Figure 1 shows internal data memory organization and SFR Memory Map. FFH FFH Special Function Registers The Special Function Registers (SFR's) are located in upper 128 Bytes direct addressing area. The SFR Memory Map in Figure 1 shows that. F8 F0 B E8 E0 ACC D8 D0 PSW C8 T2CON C0 B8 IP B0 P3 A8 IE A0 P2 98 SCON 90 P1 88 TCON 80 P0 FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 Upper 128 Accessible by Indirect Addressing Only 80H 7FH Accessible by Direct Addressing RCAP2L RCAP2H TL2 TH2 80H Lower 128 Accessible by Direct and Indirect Addressing 0 ADD SBUF TMOD SP PWM1 PWM2 Special Function Registers Ports, Status and Control Bits, Timer, Registers, Stack Pointer, Accumulator (Etc.) TL0 DPL TL1 DPH TH0 TH1 PCON Bit Addressable Figure 1. Internal Data Memory and SFR Memory Map Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect. User software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. In that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1. The functions of the SFRs are outlined in the following sections. Accumulator (ACC) ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions, however, refer to the Accumulator simply as A. B Register (B) The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad register. (July, 2002, Version 1.0) 6 AMIC Technology, Inc. A8351601 Series Program Status Word (PSW). The PSW register contains program status information. Stack Pointer (SP) The Stack Pointer Register is eight bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. Data Pointer (DPTR) The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers. Ports 0 To 3 P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively. Serial Data Buffer (SBUF) The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer. Timer Registers Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are the 16-bit Counter registers for Timer/Counters 0, 1, and 2, respectively. Capture Registers The register pair (RCAP2H, RCAP2L) are the Capture registers for the Timer 2 Capture Mode. In this mode, in response to a transition at the A8351601's T2EX pin, TH2 and TL2 are copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value for this mode. Control Registers Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections of this chapter. The detail description of each bit is as follows: PSW: Program Status Word. Bit Addressable. 7 6 CY AC Register Description: CY PSW.7 AC PSW.6 F0 PSW.5 RS1 PSW.4 RS0 PSW.3 OV PSW.2 PSW.1 P PSW.0 5 F0 4 RS1 3 RS0 2 OV 1 0 P Carry flag. Auxiliary carry flag. Flag 0 available to the user for general purpose. Register bank selector bit 1. (1) Register bank selector bit 0. (1) Overflow flag. Usable as a general purpose flag Parity flag. Set/Clear by hardware each instruction cycle to indicate an odd/even number of "1" bits in the accumulator. Note: 1. The value presented by RS0 and RS1 selects the corresponding register bank. RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 Address 00H-07H 08H-0FH 10H-17H 18H-1FH (July, 2002, Version 1.0) 7 AMIC Technology, Inc. A8351601 Series PCON: Power Control Register. Not Bit Addressable. 7 6 5 4 3 2 1 0 SMOD GF1 GF0 PD IDL Register Description: SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when the serial port is used in modes 1, 2, or 3. Not implemented, reserve for future use. (1) Not implemented, reserve for future use. (1) Not implemented, reserve for future use. (1) GF1 General purpose flag bit. GF0 General purpose flag bit. PD Power-down bit. Setting this bit activates power-down operation in the A8351601. IDL Idle mode bit. Setting this bit activates idle mode operation in the A8351601. If 1s are written to PD and IDL at the same time, PD takes precedence. Note: 1. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. IE Interrupt Enable Register. Bit Addressable. 7 6 EA Register Description: EA IE.7 ET2 ES ET1 EX1 ET0 EX0 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Not implemented, reserve for future use. (5) Enables or disables timer 2 overflow interrupt. Enable or disable the serial port interrupt. Enable or disable the timer 1 overflow interrupt. EX1 IE.2 Enable or disable external interrupt 1. Enable or disable the timer 0 overflow interrupt. Enable or disable external interrupt 0. Note: To use any of the interrupts in the 80C51 Family, the following three steps must be taken: 1. Set the EA (enable all) bit in the IE register to 1. 2. Set the corresponding individual interrupt enable bit in the IE register to 1. 3. Begin the interrupt service routine at the corresponding Vector Address of that interrupt (see below). Interrupt Source Vector Address IE0 TF0 IE1 TF1 RI & TI TF2 and EXF2 0003H 000BH 0013H 001BH 0023H 002BH 4. In addition, for external interrupts, pins INT0 and INT1 (P3.2 and P3.3) must be set to 1, and depending on whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to be set to 0 or 1. ITX = 0 level activated (X = 0, 1) ITX = 1 transition activated 5. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. (July, 2002, Version 1.0) 8 AMIC Technology, Inc. A8351601 Series IP: Interrupt Priority Register. Bit Addressable. 7 6 Register Description: IP.7 IP.6 PT2 IP.5 PS IP.4 PT1 IP.3 PX1 IP.2 PT0 IP.1 PX0 IP.0 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Not implemented, reserve for future use (3) Not implemented, reserve for future use (3) Defines Timer 2 interrupt priority level Defines Serial Port interrupt priority level Defines Timer 1 interrupt priority level Defines External Interrupt 1 priority level Defines Timer 0 interrupt priority level Defines External Interrupt 0 priority level Notes: 1. In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1. While an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt. 2. Priority within level is only to resolve simultaneous requests of the same priority level. From high to low, interrupt sources are listed below: IE0 > TF0 > IE1 > TF1 > RI or TI > TF2 or EXF2 3. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. TCON: Timer/Counter Control Register. Bit Addressable. 7 6 TF1 TR1 Register Description: TF1 IP.7 TR1 TF0 TR0 IE1 IT1 IE0 IT0 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 1 run control bit. Set/Cleared by software to turn Timer/Counter 1 ON/OFF. Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 0 run control bit. Set/Cleared by software to turn Timer/Counter 0 ON/OFF. External Interrupt 1 edge flag. Set by hardware when the External Interrupt edge is detected. Cleared by hardware when interrupt is processed. Interrupt 1 type control bit. Set/Cleared by software specify falling edge/low level triggered External Interrupt. External Interrupt 0 edge flag. Set by hardware when the External Interrupt edge is detected. Cleared by hardware when interrupt is processed. Interrupt 0 type control bit. Set/Cleared by software specify falling edge/low level triggered External Interrupt. TMOD: Timer/Counter Mode Control Register. Not Bit Addressable. GATE GATE C/ T M1 M0 Timer 1 Timer 0 C/ T M1 M0 GATE C/ T M1 M0 When TRx (in TCON) is set and GATE=1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE=0, TIMER/COUNTERx will run only while TRx=1 (software control). Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from Tx input pin). Mode selector bit. (1) Mode selector bit. (1) (July, 2002, Version 1.0) 9 AMIC Technology, Inc. A8351601 Series Note 1: M1 0 0 1 1 M0 0 1 0 1 Operating mode Mode 0. (13-bit Timer) Mode 1. (16-bit Timer/Counter) Mode 2. (8-bit auto-load Timer/Counter) Mode 3. (Splits Timer 0 into TL0 and TH0. TL0 is an 8-bit Timer/ Counter controller by the standard Timer 0 control bits. TH0 is an 8-bit Timer and is controlled by Timer 1 control bits.) Mode 3. (Timer/Counter 1 stopped). 1 SCON: 1 Serial Port Control Register. Bit Addressable. 7 6 SM0 SM1 Register Description: SM0 SCON.7 SM1 SCON.6 SM2 SCON.5 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI REN TB8 RB8 TI RI SCON.4 SCON.3 SCON.2 SCON.1 SCON.0 Serial port mode specifically. (1) Serial port mode specifically. (1) Enable the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 th is set to 1 then RI will not be activated if the received 9 data bit (RB8) is 0. In mode 1, if SM2=1 then RI will not be activated if valid stop bit was not received. In mode 0, SM2 should be 0. Set/Cleared by software to Enable/Disable reception. The 9th bit that will be transmitted in mode 2 and 3. Set/Cleared by software. In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2=0, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes (except see SM2). Must be cleared by software. MODE 0 1 2 3 Description Shift register 8-bit UART 9-bit UART 9-bit UART Baud rate Fosc/12 Variable Fosc/64 or Fosc/32 Variable Note: SM0 0 0 1 1 T2CON: SM1 0 1 0 1 Timer/Counter 2 Control Register. Bit Addressable. 7 6 TF2 EXF2 Register Description: TF2 T2CON.7 EXF2 T2CON.6 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/ T2 0 CP/ RL2 RCLK T2CON.5 TCLK T2CON.4 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. (July, 2002, Version 1.0) 10 AMIC Technology, Inc. A8351601 Series T2CON: (continued) 7 6 TF2 EXF2 Register Description: EXEN2 T2CON.3 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/ T2 0 CP/ RL2 TR2 C/ T2 CP/ RL2 T2CON.2 T2CON.1 T2CON.0 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Software START/STOP control for Timer 2. A logic 1 starts the Timer. Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling edge). Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2 =1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the Timer is forced to auto-reload on Timer 2 overflow. Notes: Timer 2 Operating Modes RCLK + TCLK CP/ RL2 0 0 0 1 1 X ADD(A1H): Extra Additional Register. Not Bit Addressable. 7 6 5 4 3 2 1 0 Delay2 Delay1 Delay0 T2EXREV DF RAMDIS Register Description: Not implemented, reserve for future use. Not implemented, reserve for future use. D2 PWM3 delay control bit. D1 PWM3 delay control bit. D0 PWM3 delay control bit. T2EXREV T2EX reverse control bit. Set/Cleared by software specify T2EX pin reverse/no reverse. DF Double system frequency control bit. Set/Cleared by software specify Xtal frequency *2 / Xtal frequency. RAMDIS Build in 8K bytes SRAM enable/disable control bit. Set/Cleared by software specify Enable/disable build in 8K bytes SRAM. Bit <5:3> Delay 0 4 CLK 1 5 CLK 2 6 CLK 3 7 CLK 4 8 CLK 5 9 CLK 6 10 CLK 7 11 CLK TR2 1 1 1 MODE 16-Bit Auto-Reload 16-Bit Capture Baud Rate Generator (D2, D1, D0) controlled the delay time of PWM3 after PWM1 change. (July, 2002, Version 1.0) 11 AMIC Technology, Inc. A8351601 Series PWM1: Pulse Width Modulation 1 Register. Not Bit Addressable. 7 6 5 4 3 2 1 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 Register Description: PWM1.7 PWM4 output control. Set/Clear by specify 75% duty/67% duty. PWM1.6 PWM1 frequency control bit. Set/Cleared by specify half/normal PWM1 frequency. PWM1.5 PWM1 cycle control bit. PWM1.4 PWM1 cycle control bit. PWM1.3 PWM1 cycle control bit. PWM1.2 PWM1 cycle positive edge width control bit. PWM1.1 PWM1 cycle positive edge width control bit. PWM1.0 PWM1 cycle positive edge width control bit. 0 PWM1.0 Note: T2 T1 PWM1 Delay 4~11 CLK T3 PWM3 3072 T3(PWM1.7:1)/2048 T3(PWM1.7:0) PWM4 1024 T3 Xtal frequency = 14.7456MHz Bit<5:3> 0 1 T1 1.017us 1.695us Bit<2:0> T2 0 542.4ns 1 67.8ns 2 2.373us 2 135.6ns 3 3.051us 3 203.4ns 4 3.729us 4 271.2ns 5 4.407us 5 339ns 6 5.085us 6 406.8ns 7 5.763us 7 474.6ns (July, 2002, Version 1.0) 12 AMIC Technology, Inc. A8351601 Series PWM2: Pulse Width Modulation 2 Register. Not Bit Addressable. 7 6 5 4 3 2 1 PWM2.7 PWM2.3 PWM2.2 PWM2.1 Register Description: PWM2.7 PWM2 output control bit. Set/Cleared by specify enable/ground PWM2. PWM2.6 Not implemented, reserve for future use. PWM2.5 Not implemented, reserve for future use. PWM2.4 Not implemented, reserve for future use. PWM2.3 PWM2 frequency control bit. Set/Cleared by specify half/normal PWM2 frequency. PWM2.2 PWM2 cycle control bit. PWM2.1 PWM2 cycle control bit. PWM2.0 PWM2 cycle control bit. Xtal frequency = 14.7456MHz Bit<2:0> 0 1 PWM2 3600Hz 2880Hz 2 2400Hz 3 2057Hz 4 1600Hz 5 1440Hz 6 1200Hz 0 PWM2.0 7 1029Hz (July, 2002, Version 1.0) 13 AMIC Technology, Inc. A8351601 Series Timer/Counters The A8351601 has three 16-bit Timer/Counter registers: Timer 0, Timer 1, and in addition Timer 2. All three can be configured to operate either as Timers or event Counters. As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. As a Counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0, T1, and T2. The external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes. In addition to the Timer or Counter functions, Timer 0 and Timer 1 have four operating modes: (13-bit timer, 16-bit timer, 8-bit auto-reload, split timer). Timer 2 in the A8351601 has three modes of operation: Capture, AutoReload, and Baud Rate Generator. Timer 0 and Timer 1 Timer/Counters 0 and 1 are present in A8351601. The Timer or Counter function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timer/ Counters, but Mode 3 is different. The four modes are described in the following sections. Mode 0: Both Timers in Mode 0 are 8-bit Counters with a divide-by 32 prescaler. Figure 2 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TF1. The counted input is enabled to the Timer when TR1= 1 and either GATE= 0 or INT1= 1. Setting GATE= 1 allows the Timer to be controlled by external input INT1 , to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register TCON. Gate is in TMOD. The 13-bit register consists of all eight bits of TH1 and the lower five bits of TL1. The upper three bits of TL1 are indeterminate and should be ignored. Setting the run flag (TR1) does not clear the registers. Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0 and INT0 replace the corresponding Timer 1 signals in Figure 2. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3). ONE MACHINE CYCLE OSC (XTAL2) S1 P1 P2 S2 P1 P2 S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 S1 P1 P2 S2 P1 P2 ONE MACHINE CYCLE S3 P1 P2 S4 P1 P2 S5 P1 P2 S6 P1 P2 S1 P1 P2 OSC DIVIDE 12 C/T=0 T1 PIN TR1 GATE TL1 (5 BITS) CONTROL TH1 (8 BITS) TF1 INTERRUPT C/T=1 INT1 PIN Figure 2. Timer/Counter 1 Mode 0: 13-Bit Counter TIMER CLOCK TL1 (8 BITS) TH1 (8 BITS) TF1 OVERFLOW FLAG Figure 3. Timer/Counter 1 Mode 1: 16-Bit Counter (July, 2002, Version 1.0) 14 AMIC Technology, Inc. A8351601 Series Mode 1: Mode 1 is the same as Mode 0, except that the Timer register is run with all 16 bits. The clock is applied to the combined high and low timer registers (TL1/TH1). As clock pulses are received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-0000H overflow flag. The timer continues to count. The overflow flag is the TF1 bit in TCON that is read or written by software (see Figure 3). Mode 2: Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 4. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves the TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0. Mode 3: Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 4. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, INT0 , and TF0. TH0 is locked into a timer function (counting machine cycles) and over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the A8351601 can appear to have four. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. OSC DIVIDE 12 C/T=0 TL1 (8 BITS) CONTROL TR1 GATE INT1 PIN TH1 (8 BITS) RELOAD TF1 INTERRUPT T1 PIN C/T=1 Figure 4. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload OSC DIVIDE 2 1/12F OSC 1/12F OSC C/T=0 C/T=1 CONTROL TR0 TL0 (8 BITS) TF0 INTERRUPT T0 PIN GATE INT0 PIN 1/12F OSC TR1 CONTROL TH0 (8 BITS) TF1 INTERRUPT Figure 5. Timer/Counter 0 Mode 3: Two 8-Bit Counters (July, 2002, Version 1.0) 15 AMIC Technology, Inc. A8351601 Series Timer 2 Timer 2 is a 16-bit Timer/Counter present only in the A8351601. This is a powerful addition to the other two just discussed. Five extra special function registers are added to accommodate Timer 2 which are: the timer registers, TL2 and TH2, the timer control register, T2CON, and the capture registers, RCAP2L and RCAP2H. Like Timers 0 and 1, it can operate either as a timer or as an event counter, depending on the value of bit C/T2 in the Special Function Register T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator, which are selected by RCLK, TCLK, CP/ RL2 and TR2. In the Capture Mode, the EXEN2 bit in T2CON selects two options. If EXEN2=0, then Timer 2 is a 16-bit timer or counter whose overflow sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2=1, then Timer 2 performs the same way, but a 1to-0 transition at external input T2EX also causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into the RCAP2L and RCAP2H registers, respectively. In addition, the transition at T2EX sets the EXF2 bit in T2CON, and EXF2, like TF2, can generate an interrupt. The Capture Mode is illustrated in Figure 6. In the auto-reload mode, the EXEN2 bit in T2CON also selects two options. If EXEN2 = 0, then when Timer 2 rolls over it sets TF2 and also reloads the Timer 2 registers with the 16-bit value in the RCAP2L and RCAP2H registers, which are preset by software. If EXEN2 = 1, then Timer 2 performs the same way, but a 1-to-0 transition at external input T2EX also triggers the 16-bit reload and sets EXF2. The auto-reload mode is illustrated in Figure 7. The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. This mode is described in conjunction with the serial port (Figure 8). OSC DIVIDE 12 C/T2=0 TL2 (8 BITS) TH2 (8 BITS) TF2 T2 PIN C/T2=1 CONTROL TR2 CAPTURE TRANSITION DETECTOR TIMER 2 INTERRUPT RCAP2L RCAP2H T2EX PIN CONTROL EXEN2 EXF2 Figure 6. Timer 2 in Capature Mode (July, 2002, Version 1.0) 16 AMIC Technology, Inc. A8351601 Series OSC DIVIDE 12 C/T2=0 TL2 TH2 (8 BITS) (8 BITS) T2 PIN C/T2=1 CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER 2 INTERRUPT EXF2 CONTROL EXEN2 T2EX PIN Figure 7. Timer 2 in Auto-Reload Mode TIMER 1 OVERFLOW NOTE:OSC FREQ. IS DIV BY 2, NOT 12 DIVIDE 2 "0" "1" SMOD TL2 (8 BITS) TH2 (8 BITS) "1" "0" RCLK DIVIDE 16 RELOAD "1" "0" RX CLOCK TX CLOCK OSC DIVIDE 12 C/T2=0 T2 PIN C/T2=1 CONTROL TR2 TCLK TRANSITION DETECTOR T2EX PIN EXF2 CONTROL EXEN2 RCAP2L RCAP2H DIVIDE 16 TIMER 2 INTERRUPT Figure 8. Timer 2 in Baud Rate Generator Mode Note: 1. T2EX can be used as an additional external interrupt. (July, 2002, Version 1.0) 17 AMIC Technology, Inc. A8351601 Series Timer Set-Up Tables 3 through 6 give TMOD values that can be used to set up Timers in different modes. It assumes that only one timer is used at a time. If Timers 0 and 1 must run simultaneously in any mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6). For example, if Timer 0 must run in Mode 1 GATE (external control), and Timer 1 must run in Mode 2 COUNTER, then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6). Moreover, it is assumed that the user is not ready at this point to turn the timers on and will do so at another point in the program by setting bit TRx (in TCON) to 1. Table 3. Timer/Counter 0 Used as a Timer TMOD Mode 0 1 2 3 Timer 0 Function 13-Bit Timer 16-Bit Timer 8-Bit Auto-Reload Two 8-Bit timers Internal (1) Control 00H 01H 02H 03H External (2) Control 08H 09H 0AH 0BH Mode 0 1 2 3 Timer 1 Function 13-Bit Timer 16-Bit Timer 8-Bit Auto-Reload Not Available Table 5. Timer/Counter 1 Used as a Timer TMOD Mode 0 1 2 3 Timer 1 Function 13-Bit Timer 16-Bit Timer 8-Bit Auto-Reload Does Not Run Internal (1) Control 00H 10H 20H 30H External (2) Control 80H 90H A0H B0H Table 6. Timer/Counter 1 Used as a Timer TMOD Internal (1) Control 40H 50H 60H External (2) Control C0H D0H E0H - Table 4. Timer/Counter 0 Used as a Counter TMOD Mode 0 1 2 3 Timer 0 Function 13-Bit Timer 16-Bit Timer 8-Bit Auto-Reload One 8-Bit Counter Internal (1) Control 04H 05H 06H 07H External (2) Control 0CH 0DH 0EH 0FH Notes: 1. The Timer is turned ON/OFF by setting/clearing bit TR1 in the software. 2. The Timer is turned ON/OFF by the 1 to 0 transition on INT1 (P3.3) when TR1 = 1 (hardware control). Notes: 1. The Timer is turned ON/OFF by setting/clearing bit TR0 in the software. (July, 2002, Version 1.0) 18 AMIC Technology, Inc. A8351601 Series Timer/Counter 2 Set-Up Except for the baud rate generator mode, the values given for T2C0N do not include the setting of the TR2 bit. Therefore, bit TR2 must be set separately to turn the Timer on. Table 7. Timer/Counter 2 Used as a Timer T2CON Mode 16-Bit Auto-Reload 16-Bit Capture Baud Rate Generator Receive and Transmit Same Baud Rate Receive Only Transmit Only Internal (1) Control 00H 01H 34H 24H 14H External (2) Control 08H 09H 36H 26H 16H Serial Interface The Serial port is full duplex, which means it can transmit and receive simultaneously. It is also receive-buffered, which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (However, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The serial port can operate in the following four modes: Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/12 the oscillator frequency (see Figure 9). Mode 1: Table 8. Timer/Counter 2 Used as a Counter T2CON Mode 16-Bit Auto-Reload 16-Bit Capture Internal (1) Control 02H 03H External (2) Control 0AH 0BH Ten bits are transmitted (through TXD) or received (through RXD): a start bit (0), eight data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable (see Figure 10). Mode 2: Eleven bits are transmitted (through TXD) or received (through RXD): a start bit (0), eight data bits (LSB first), a programmable ninth data bit, and a stop bit (1). On transmit, the ninth data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) can be moved into TB8. On receive, the ninth data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency (see Figure 11). Mode 3: Eleven bits are transmitted (through TXD) or received (through RXD): a start bit (0), eight data bits (LSB first), a programmable ninth data bit, and a stop bit (1). In fact, Mode 3 is the same as Mode 2 in all respects except the baud rate, which is variable in Mode 3 (see Figure 12). In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. Notes: 1. Capture/Reload occurs only on Timer/Counter overflow. 2. Capture/Reload occurs on Timer/Counter overflow and a 1 to 0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode. (July, 2002, Version 1.0) 19 AMIC Technology, Inc. A8351601 Series Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, nine data bits are received, followed by a stop bit. The ninth bit goes into RB8; then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt is activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. The following example shows how to use the serial interrupt for multiprocessor communications. When the master processor must transmit a block of data to one of several slaves, it first sends out an address byte that identifies the target slave. An address byte differs from a data byte in that the ninth bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave is interrupted by a data byte. An address byte, however, interrupts all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave clears its SM2 bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes. SM2 has no effect in Mode 0 but can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received. Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation. Oscillator Frequency Mode 0 Baud Rate = 12 The baud rate in Mode 2 depends on the value of the SMOD bit in Special Function Register PCON. If SMOD= 0 (the value on reset), the baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the baud rate is 1/32 of the oscillator frequency, as shown in the following equation. Mode 2 Baud Rate = 2 SMOD Using the Timer 1 to Generate Baud Rates When Timer 1 is the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD according to the following equation. Mode 1,3 Baud Rate = 2 SMOD X (Timer 1 Overflow Rate) 32 The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter operation in any of its 3 running modes. In the most typical applications, it is configured for timer operation in auto-reload mode (high nibble of TMOD =0010B). In this case, the baud rate is given by the following formula. Mode 1,3 Baud Rate = 2 SMOD X 32 Programmers can achieve very low baud rates with Timer 1 by leaving the Timer 1 interrupt enabled, configuring the Timer to run as a 16-bit timer (high nibble of TMOD =0001B), and using the Timer 1 interrupt to do a 16-bit software reload. Table 9 lists commonly used baud rates and how they can be obtained from Timer 1. Oscillator Frequency 12 X [256-(TH1)] X (Oscillator Frequency) 64 In the A8351601, the baud rates can be determined by Timer 1, Timer 2, or both (one for transmit and the other for receive). (July, 2002, Version 1.0) 20 AMIC Technology, Inc. A8351601 Series Using Timer 2 to Generate Baud Rates In the A8351601, setting TCLK and/or RCLK in T2CON selects Timer 2 as the baud rate generator. Under these conditions, the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 8. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 reloads the Timer 2 registers with the 16-bit value in the RCAP2H and RCAP2L registers, which are preset by software. In this case, the baud rates in Mode 1 and 3 are determined by the Timer 2 overflow rate according to the following Equation. Timer 2 Overflow Rate 16 Timer 2 can be configured for either timer or counter operation. In the most typical applications, it is configured for timer operation (C/ T2= 0). Normally, a timer increments every machine cycle (thus at 1/12 the oscillator frequency), but timer operation is a different for Timer 2 when it is used as a baud rate generator. As a baud rate generator, Timer 2 increments every state time (thus at 1/2 the oscillator frequency). In this case, the baud rate is given by the following formula. Modes 1,3 Baud Rate Oscillator Frequency 32 X [65536 - (RCAP2H, RCAP2L)] Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Figure 7 shows Timer 2 as a baud rate generator. This figure is valid only if RCLK + TCLK = 1 in T2CON. A rollover in TH2 does not set TF2 and does no generate an interrupt. Therefore, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. If EXEN2 is set, a 1-to-0 transition in T2EX sets EXF2 but does not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is used as a baud rate generator, T2EX can be used as an extra external interrupt. When Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, programmers should not read from or write to TH2 or TL2. Under these conditions, Timer 2 is incremented every state time, and the results of a read or write may not be accurate. The RCAP registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. Turn Timer 2 off (clear TR2) before accessing the Timer 2 or RCAP registers, in this case. Modes 1,3 Baud Rate = = Table 9. Commonly Used Baud Rates Generated by Timer 1 Baud Rate Mode 0 Max: 1 MHz Mode 2 Max: 375K Modes 1,3: 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 110 110 fOSC 12 MHz 12 MHz 12 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.059 MHz 11.986 MHz 6 MHz 12 MHz SMOD C/ T X 1 1 1 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0 Timer 1 Mode X X 2 2 2 2 2 2 2 2 1 Reload Value X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH (July, 2002, Version 1.0) 21 AMIC Technology, Inc. A8351601 Series More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/12 the oscillator frequency. Figure 9 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal at S6P2 also loads a 1 into the ninth position of the transmit shift register and tells the TX Control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between "write to SBUF" and activation of SEND. SEND transfer the output of the shift register to the alternate output function line of P3.0, and also transfers SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift register are shifted one position to the right. As data bits shift out to the right, 0s come in from the left. When the MSB of the data byte is at the output position of the shift register, the 1 that was initially loaded into the ninth position is just to the left of the MSB, and all positions to the left of that contain 0s. This condition flags the TX Control block to do one last shift, then deactivate SEND and set TI. Both of these actions occur at S1P1 of the tenth machine cycle after "write to SBUF." Reception is initiated by the condition REN = 1 and RI = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next clock phase. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of every machine cycle in which RECEIVE is active, the contents of the receive shift register are shifted on position to the left. The value that comes in from the right is the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle. As data bits come in from the right, 1s shift out to the left. When the 0 that was initially loaded into the right-most position arrives at the left-most position in the shift register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set. More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), eight data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the A8351601 the baud rate is determined either by the Timer 1 overflow rate, the Timer 2 overflow rate, or both. In this case, one Timer is for transmit, and the other is for receive. Figure 10 shows a simplified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to =SBUF" signal also loads a 1 into the ninth bit position of the transmit shift register and flags the TX control unit that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal. The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, 0s are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, the 1 that was initially loaded into the ninth position is just to the left of the MSB, and all positions to the left of that contain 0s. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the tenth divide-by-16 rollover after "write to SBUF". Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16th. At the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least two of the three samples. This is done to reject noise. In order to reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. If the start bit is valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. (July, 2002, Version 1.0) 22 AMIC Technology, Inc. A8351601 Series As data bits come in from the right, 1s shift to the left. When the start bit arrives at the leftmost position in the shift register, (which is a 9-bit register in Mode 1), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. RI = 0 and 2. Either SM2 = 0, or the received stop bit =1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the eight data bits go into SBUF, and RI is activated. At this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0 transition in RXD. More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable ninth data bit, and a stop bit (1). On transmit, the ninth data bit (TB8) can be assigned the value of 0 or 1. On receive, the ninth data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or 2, depending on the state of TCLK and RCLK. Figures 11 and 12 show a functional diagram of the serial port in Modes 2 and 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only in the ninth bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The "write to SBUF" signal also loads TB8 into the ninth bit position of the transmit shift register and flags the TX Control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by16 counter. Thus, the bit times are synchronized to the divide-by-16 counter, not to the "write to SBUF" signal. The transmission begins when SEND is activated, which puts the start bit at TXD. One bit timer later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the ninth bit position of the shift register. Thereafter, only 0s are clocked in. Thus, as data bits shift out to the right, 0s are clocked in from the left. When TB8 is at the output position of the shift register, then the stop bit is just to the left of TB8, and all positions to the left of that contain 0s. This condition flags the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the 11th divide-by-16 rollover after "write to SBUF". Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the seventh, eighth, and ninth counter states of each bit time, the bit detector samples the value of RXD. The value accepted is the value that was seen in at least two of the three samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit continues looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame proceeds. As data bits come in from the right, Is shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the RX Control block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8 and to set RI is generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1. RI = 0, and 2. Either SM2 = 0 or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received ninth data bit goes into RB8, and the first eight data bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit continues looking for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. Table 10. Serial Port Setup Mode 0 1 2 3 0 1 2 3 SCON 10H 50H 90H D0H NA 70H B0H F0H Multiprocessor Environment (SM2=1) Single Processor Environment (SM2=0) SM2Variation (July, 2002, Version 1.0) 23 AMIC Technology, Inc. A8351601 Series Serial Port Mode 0 WRITE TO SBUF DQ CL S SBUF SHIFT ZERO DETECTOR RXD P3.0 ALT OUTPUT FUNCTION START S6 SERIAL PORT INTERRUPT TX CONTORL TX CLOCK SHIFT SEND TXD P3.1 ALT OUTPUT FUNCTION SHIFT CLOCK RX CLOCK REN RI START RI RECEIVE RX CONTORL SHIFT 11111110 RXD P3.0 ALT INPUT FUNCTION INPUT SHIFT REG. LOAD SBUF SHIFT SBUF READ SBUF A8351601 INTERNAL BUS S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 ALE WRITE TO SBUF SEND SHIFT RXD (DOUT) S6P2 D0 D1 D2 D3 D4 D5 D6 D7 TRANSMIT TXD (SHIFT CLOCK) S3P1 S6P1 TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DIN) S5P2 RECEIVE TXD (SHIFT CLOCK) Figure 9. Serial Port Mode 0 (July, 2002, Version 1.0) 24 AMIC Technology, Inc. A8351601 Series Serial Port Mode 1 TIMER1 OVERFLOW A8351601 INTERNAL BUS TIMER2 OVERFLOW WRITE TO SBUF TB8 /2 SMOD =0 SMOD =1 DS Q CL SBUF ZERO DETECTOR TXD "0" TCLK "0" RCLK "1" / 16 START SHIFT DATA TX CONTORL RX CLOCK TI SEND SERIAL PORT INTERRUPT "1" / 16 SAMPLE 1-TO-0 TRANSITION DETECTOR LOAD RX CLOCK RI SBUF RX CONTORL SHIFT START 1FFH BIT DETECTOR RXD LOAD SBUF INPUT SHIFT REG. (9SBITS) SHIFT SBUF READ SBUF A8351601 INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD TI RX CLOCK RXD RECEIVE BIT DETECTOR SAMPLE TIMES / 16 RESET S1P1 TRANSMIT START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT SHIFT RI Figure 10. Serial Port Mode 1 (July, 2002, Version 1.0) 25 AMIC Technology, Inc. A8351601 Series Serial Port Mode 2 A8351601 INTERNAL BUS TB8 WRITE TO SBUF S D Q CL SBUF ZERO DETECTOR TXD PHASE 2 CLOCK (1/2 fosc) MODE 2 SMOD1 / 16 STOP BIT GEN SHIFT DATA START TX CONTORL SEND TI TX CLOCK /2 SMOD0 (SMOD IS PCON.7) SAMPLE 1-TO-0 TRANSITION DETECTOR / 16 RX CLOCK RI RX CONTORL START LOAD SBUF SHIFT 1FFH SERIAL PORT INTERRUPT BIT DETECTOR RXD LOAD SBUF INPUT SHIFT REG. (9 BITS) SHIFT SBUF READ SBUF A8351601 INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD TI STOP BIT GEN RX CLOCK RXD RECEIVE / 16 RESET S1P1 TRANSMIT START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT START BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT BIT DETECTOR SAMPLE TIMES SHIFT RI Figure 11. Serial Port Mode 2 (July, 2002, Version 1.0) 26 AMIC Technology, Inc. A8351601 Series Serial Port Mode 3 TIMER1 OVERFLOW A8351601 INTERNAL BUS TIMER2 OVERFLOW WRITE TO SBUF TB8 /2 SMOD =0 SMOD =1 DS CL Q SBUF ZERO DETECTOR TXD "0" TCLK "0" RCLK "1" / 16 START SHIFT DATA TX CONTORL SEND RX CLOCK TI "1" / 16 SERIAL PORT INTERRUPT LOAD SBUF SHIFT 1FFH SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTORL BIT DETECTOR RXD LOAD SBUF INPUT SHIFT REG. (9 BITS) SHIFT SBUF READ SBUF A8351601 INTERNAL BUS TX CLOCK WRITE TO SBUF SEND DATA SHIFT TXD TI STOP BIT GEN RX CLOCK RXD RECEIVE BIT DETECTOR SAMPLE TIMES / 16 RESET S1P1 TRANSMIT START BIT D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP BIT START BIT D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP BIT SHIFT RI Figure 12. Serial Port Mode 3 (July, 2002, Version 1.0) 27 AMIC Technology, Inc. A8351601 Series Interrupt System The A8351601 provides six interrupt sources: two external interrupts, three timer interrupts, and a serial port interrupt. These are shown in Figure 13. The External Interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source (rather than the on-chip hardware) controls the request flag. The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to. The Serial Port Interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine normally must determine whether RI or TI generated the interrupt, and the bit must be cleared in software. In the A8351601, the Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether TF2 or EXF2 generated the interrupt, and the bit must be cleared in software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (interrupt enable) at address 0A8H. As well as individual enable bits for each interrupt source, there is a global enable/disable bit that is cleared to disable all interrupts or set to turn on interrupts (see SFR IE). POLLING HARDWARE TCON.1 INT0 EXTERNAL INT RQST 0 IE0 TCON.5 TIMER/COUNTER 0 TF0 TCON.3 INT1 EXTERNAL INT RQST 1 IE1 TCON.7 TIMER/COUNTER 1 TF1 INTERNAL SERIAL PORT SCON.0 RI SCON.1 TI T2CON.7 TF2 T2CON.6 EXF2 IE.0 IE.7 IP.0 HIGH PRIORITY INTERRUPT REQUEST EX0 IE.1 PX0 IP.1 ET0 IE.2 PT0 IP.2 SOURCE I.D. VECTOR EX1 IE.3 PX1 IP.3 ET1 IE.4 PT1 IP.4 LOW PRIORITY INTERRUPT REQUEST ES IE.5 PS IP.5 SOURCE I.D. T2EX TIMER/ COUNTE2 VECTOR ET2 EA PT2 Figure 13. Interrupt System (July, 2002, Version 1.0) 28 AMIC Technology, Inc. A8351601 Series Priority Level Structure Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Register IP (interrupt priority) at address 0B8H. IP is cleared after a system reset to place all interrupts at the lower priority level by default. A low-priority interrupt can be interrupted by a high-priority interrupt but not by another low-priority interrupt. A high-priority interrupt can not be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence, as follows: Source IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 Priority Within Level (Highest) in the Response Timer Section). If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to the appropriate service routine, provided this hardware generated LCALL is not blocked by any of the following conditions: 1. An interrupt of equal or higher priority level is already in progress. 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any write to the IE or IP registers. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. Condition 3 ensures that if the instruction in progress is RETI or any access to IE or IP, then at least one more instruction will be executed before any interrupt is vectored to. The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. If an active interrupt flag is not being serviced because of one of the above conditions and is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag was once active but not serviced is not remembered. Every polling cycle is new. The polling cycle/LCALL sequence is illustrated in Figure 14. Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 14, then in accordance with the above rules it will be serviced during C5 and C6, without any instruction of the lower priority routine having been executed. 1. 2. 3. 4. 5. 6. (Lowest) Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level. How Interrupts Are Handled The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle (the Timer 2 interrupt cycle is different, as described C1 S5P2 S6 C2 C3 C4 C5 ~ ~ ~ ~ E INTERRUPT GOES ACTIVE INTERRUPT LATCHED INTERRUPTS ARE POLLED LONG CALL TO INTERRUPT VECTOR ADDRESS INTERRUPT ROUTINE Figure 14. Interrupt Response Timing Diagram (July, 2002, Version 1.0) 29 AMIC Technology, Inc. ~ ~ A8351601 Series Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL to the appropriate servicing routine. In some cases it also clears the flag that generated the interrupt, and in other cases it does not. It never clears the Serial Port or Timer 2 flags. This must be done in the user's software. The processor clears an external interrupt flag (IE0 or IE1) only if it was transition-activated. The hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being serviced, as follows: Interrupt Source Interrupt Request Bits IE0 TF0 IE1 TF1 RI, TI TF2, EXF2 RST Cleared by Hardware No (level) Yes (trans.) Yes No (level) Yes (trans.) Yes No No Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0000H When an interrupt is accepted the following action occurs: 1. The current instruction completes operation. 2. The PC is saved on the stack. 3. The current interrupt status is saved internally. 4. Interrupts are blocked at the level of the interrupts. 5. The PC is loaded with the vector address of the ISR (interrupts service routine). 6. The ISR executes. The ISR executes and takes action in response to the interrupt. The ISR finishes with RETI (return from interrupt) instruction. This retrieves the old value of the PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off. External Interrupts The external sources can be programmed to be levelactivated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx= 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then the external source must deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. Response Time The INT0 and INT1 levels are inverted and latched into the interrupt flags IE0 and IE1 at S5P2 of every machine cycle. Similarly, the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at S5P2. The values are not actually polled by the circuitry until the next machine cycle. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows. INT0 Timer 0 INT1 Timer 1 Serial Port Timer 2 System Reset Execution proceeds from that location until the RETI instruction is encountered. The RETI instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the Program Counter. Execution of the interrupted program continues from where it left off. Note that a simple RET instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress. Interrupt External 0 External 1 Timer 1 Timer 0 Serial Port Serial Port TF2 Timer 2 Flag IE0 IE1 TF1 TF0 TI RI T2CON.7 EXF2 SFR Register and Bit Position TCON.1 TCON.3 TCON.7 TCON.5 SCON.1 SCON.0 Timer 2 T2CON.6 (July, 2002, Version 1.0) 30 AMIC Technology, Inc. A8351601 Series If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapsed between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 13 shows response timings. A longer response time results if the request is blocked by one of the three previously listed conditions. If an interrupt of equal or higher priority level is already in progress, the additional wait time depends on the nature of the other interrupt's service routine. If the instruction in progress is not in its final cycle, the additional wait time cannot be more than three cycles, since the longest instructions (MUL and DIV) are only four cycles long. If the instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than five cycles (a maximum of one more cycle to complete the instruction in progress, plus four cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than three cycles and less than nine cycles. Table 11. Reset Values of the SFR's SFR Name PC ACC B PSW SP DPTR P0-P3 IP IE TMOD TCON T2CON TH0 TL0 TH1 TL1 TH2 TL2 RCAP2H RCAP2L SCON SBUF PCON ADD PWM1 PWM2 Reset Value 0000H 00H 00H 00H 07H 0000H FFH XX000000B 0X000000B 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Indeterminate 0XXX0000B XXXXX000B X0000000B 0XXX0000B Other Information Reset The reset input is the RST pin, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. The CPU responds by generating an internal reset, with the timing shown in Figure 15. The external reset signal is asynchronous to the internal clock. The RST pin is sampled during State 5 Phase 2 of every machine cycle. The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin; that is, for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin. The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. Table 11 lists the SFRs and their reset values. Then internal RAM is not affected by reset. On power-up the RAM content is indeterminate. (July, 2002, Version 1.0) 31 AMIC Technology, Inc. A8351601 Series Power-on Reset An automatic reset can be obtained when VCC goes through a 10F capacitor and GND through an 8.2K resistor, providing the VCC rise time does not exceed 1 msec and the oscillator start-up time does not exceed 10 msec. This power-on reset circuit is shown in Figure 15. The CMOS devices do not require the 8.2K pulldown resistor, although its presence does no harm. When power is turned on, the circuit holds the RST pin high for an amount of time that depends on the value of the capacitor and the rate at which it charges. To ensure a good reset, the RST pin must be high long enough to allow the oscillator time to start-up (normally a few msec) plus two machine cycles. Note that the port pins will be in a random state until the oscillator has start and the internal reset algorithm has written 1s to them. With this circuit, reducing VCC quickly to 0 causes the RST pin voltage to momentarily fall below 0V. However, this voltage is internally limited, and will not harm the device. VCC 10uF + VCC A8351601 RST 8.2K GND Figure 15. Power-on Reset Circuit 12 OSC. PERIODS S5 RST INTERNAL RESET SIGNAL SAMPLE RST ALE SAMPLE RST S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 PSEN P0 INST ADDR INST ADDR INST ADDR INST ADDR INST ADDR 11 OSC. PERIODS 19 OSC. PERIODS Figure 16. Reset Timing (July, 2002, Version 1.0) 32 AMIC Technology, Inc. A8351601 Series Power-Saving Modes of Operation The A8351601 has two power-reducing modes. Idle and Power-down. The input through which backup power is supplied during these operations is VCC. Figure 17 shows the internal circuitry which implements these features. In the Idle mode (IDL = 1), the oscillator continues to run and the Interrupt, Serial Port, and Timer blocks continue to be clocked, but the clock signal is gated off to the CPU. In Power-down (PD = 1), the oscillator is frozen. The Idle and Power-down modes are activated by setting bits in Special Function Register PCON. Idle Mode An instruction that sets PCON.0 is the last instruction executed before the Idle mode begins. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the Interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into Idle. The flag bits GF0 and GF1 can be used to indicate whether an interrupt occurred during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset must be held active for only two machine cycles (24 oscillator periods) to complete the reset. The signal at the RST pin clears the IDL bit directly and asynchronously. At this time, the CPU resumes program execution from where it left off; that is, at the instruction following the one that invoked the Idle Mode. As shown in Figure 16, two or three machine cycles of program execution may take place before the internal reset algorithm takes control. On-chip hardware inhibits access to the internal RAM during his time, but access to the port pins is not inhibited. To eliminate the possibility of unexpected outputs at the port pins, the instruction following the one that invokes Idle should not write to a port pin or to external data RAM. XTAL2 OSC XTAL1 INTERRUPT, SERIAL PORT, TIMER BLOCKS CPU PD CLOCK GEN IDL Figure 17. Idle and Power-Down Hardware Power-down Mode An instruction that sets PCON.1 is the last instruction executed before Power-down mode begins. In the Power down mode, the on-chip oscillator stops. With the clock frozen, all functions are stopped, but the on-chip RAM and Special function Registers are held. The port pins output the values held by their respective SFRs. ALE and PSEN output high. In the Power-down mode of operation, VCC can be reduced to as low as 2V. However, VCC must not be reduced before the Power-down mode is invoked, and VCC must be restored to its normal operating level before the Power-down mode is terminated. The reset that terminates Power-down also frees the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (normally less than 10 msec). Reset redefines all the SFRs but does not change the onchip RAM. (July, 2002, Version 1.0) 33 AMIC Technology, Inc. A8351601 Series Oscillator Characteristics The oscillator connections are shown as Figure 18 and Figure 19. When external clock is used, the internal clock will be gotten through a divide-by-two flip-flop. Crystal 16MHz 32MHz 40MHz C1 20P 5P 5P C2 20P 5P 5P R 3KU 2KU (Above table shows the reference values for crystal applications) Note:C1,C2,R components refer to Figure 18. N/C EXTERNAL OSCILLATOR SIGNAL XTAL 2 XTAL 1 GND Figure 19. External Clock Drive configuration (July, 2002, Version 1.0) 34 AMIC Technology, Inc. A8351601 Series Recommended DC Operating Conditions (TA = -10C to + 70C, VCC = 5V 10% or VCC = 3V 10%) Symbol VCC Parameter Supply Voltage (VCC= 5V 10%) VCC Supply Voltage (VCC= 3V 10%) GND VIH* VIL Ground Input High Voltage Input Low Voltage 0 2.4 0 0 0 VCC+0.2 0.6 V V V 2.7 3.0 3.3 V Min. 4.5 Typ. 5.0 Max. 5.5 Unit V * XTAL1 is a CMOS input. RESET is a Schmitt Trigger input. The min. of VIH is 3.5 Volts for these two pins. Absolute Maximum Ratings* VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V IN, IN/OUT Volt to GND . . . . . . . . . -0.5V to VCC + 0.5V Operating Temperature, Topr . . . . . . . -25C to + 85C Storage Temperature, Tstg . . . . . . . . . -55C to + 125C 1* Power Dissipation , Pr . . . . . . . . . . . . . . . . . . . . . . 1W Soldering Temperature & Time . . . . . . . . . 260C, 10sec 1* : Operating frequency is 40MHz(5V 10%) 2* : Operating frequency is 16MHz(3V 10%) *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (TA = -10C to + 70C, VCC = 5V 10% or VCC = 3V 10%) Symbol ILI ILO ICC1 Parameter Input Leakage Current Output Leakage Current Operating Current Min. Max. 2 2 50 Unit A A mA Conditions VIN = GND to VCC VI/O = GND to VCC foper = 40MHz(DF=0) External oscillator is on XTAL1 pin No load (VCC= 5V) foper = 16MHz(DF=0) External oscillator is on XTAL1 pin No load (VCC= 3V) fidle = 14.7456MHz(DF=0) External oscillator is on XTAL1 pin No load (VCC= 5V) fidle = 14.7456MHz(DF=0) External oscillator is on XTAL1 pin No load (VCC= 3V) ICC2 Operating Current - 15 mA IIDLE1 Idle Mode Current - 6 mA IIDLE2 Idle Mode Current - 3 mA (July, 2002, Version 1.0) 35 AMIC Technology, Inc. A8351601 Series DC Electrical Characteristics (continued) Symbol IPOWER Parameter Power Down Mode Current Min. Max. 4 Unit A Conditions fpower =14.7456MHz(DF=0) External oscillator is on XTAL1 pin No load (VCC= 5V) fpower = 14.7456MHz(DF=0) External oscillator is on XTAL1 pin No load (VCC= 3V) IOL = 4mA IOH = -70A (VCC= 5V ) IOH = -12A (VCC= 3V ) IOH = -400A (VCC= 5V ) IOH = -200A (VCC= 3V ) 1MHZ , 25C IPOWER Power Down Mode Current - 2 A VOL VOH1 Output Low Voltage (ALE, PSEN, PWM,P0,P1,P2,P3) Output High Voltage (P0, P1, P2, P3) Output High Voltage (P0, P1, P2, P3) Output High Voltage (ALE, PSEN, PWM , P0,P2) Output High Voltage (ALE, PSEN , PWM , P0,P2) Input Pin Capacitance 2.4 0.45 - V V VOH1 2.4 - V VOH2 VOH2 C1 1 2.4 2.4 - 10 V V pF 1 1. P0, P2, ALE and /PSEN are tested in the external access mode. (July, 2002, Version 1.0) 36 AMIC Technology, Inc. A8351601 Series AC Characteristics (TA = -10C to + 70C, VCC = 5V 10% or VCC = 3V 10%) Symbol Program Memory Cycle tAP tALS tALH top tAO tOI 2 Parameter Min. Max. Unit ALE Pulse Width Address Valid to ALE Low Address Hold from ALE Low 2tck - 20 1tck 1tck 3tck - 20 1tck - 1 - ns ns ns ns ns ns ns ns PSEN Pulse Width ALE Low to PSEN Low 1 2tck 1tck 1tck PSEN Low to Valid Instruction in Input Instruction Hold after PSEN High Input Instruction Float after PSEN High Clock Frequency (VCC =5V 10%) Clock Frequency (VCC =3V 10%) Clock Period Clock High Time Clock Low Time tIDO tIFO External Clock(VCC =5V 10% or VCC = 3V 10%) fOPER fOPER tCK 3 4 0 0 25 10 10 1 40 16 - MHZ MHZ ns ns ns tCKH tCKL 4 Data Memory Cycle tPR tPD tDHR tDFR tAR tWP tDS tDHW tAW Serial Port Cycle tSCK tKI tIKH tOKS tOKH 1. 2. 3. 4. Serial Port Clock Clock Rising Edge to Valid Input Data Input Data to Serial Clock Rising Clock Hold Time Output Data to Serial Clock Rising Edge Setup Time Output Data to Serial Clock Rising Edge Hold Time 12tck 0 11tck 1tck 11tck ns ns ns ns ns RD Pulse Width RD Low to Valid Data in Data Hold from RD High Data Float from RD High ALE Low to RD Low 6tck - 20 0 0 3tck 6tck - 20 1tck 1tck 3tck 4tck 2tck 2tck 3tck + 20 1 ns ns ns ns ns ns ns ns 1 WR Pulse Width Valid Data to WR Low Data Hold from WR High ALE Low to WR Low 1 3tck + 20 ns This 20 ns is due to buffer driving delay and wire loading. Instruction cycle time is 12 tck. tck = 1/ foper There are no duty cycle requirements on the XTAL1 input. (July, 2002, Version 1.0) 37 AMIC Technology, Inc. A8351601 Series Timing Waveforms Program Memory Cycle S1 S2 S3 S4 S5 S6 S1 XTAL 1 tAP ALE tAO PSEN tOP tALS PORT 2 tALH A8 - A15 tOI tIHO tIFO A8 - A15 PORT 0 A0 - A7 INSTRUCTION IN A0 - A7 INSTRUCTION IN Clock Input Waveform XTAL 1 tCKH tCKL tCK (July, 2002, Version 1.0) 38 AMIC Technology, Inc. A8351601 Series Timing Waveforms (continued) Data Memory Read Cycle S4 XTAL 1 ALE PSEN PORT 2 PORT 0 RD tRP A0-A7 tAR A8-A15 DATA IN tDHR tDFR A0-A7 S5 S6 S1 S2 S3 S4 S5 S6 tRD Data Memory Write Cycle S4 XTAL 1 ALE PSEN PORT 2 PORT 0 WR S5 S6 S1 S2 S3 S4 S5 S6 A8-A15 A0-A7 tDS DATA OUT tDHW tAW tWP Serial Port Timing - Shift Register Mode 0 1 2 3 4 5 6 7 8 INSTRUCTION ALE CLOCK tSCK tOKS tOKH 1 tKI tIKH SET TI VALID VALID VALID VALID VALID VALID VALID OUTPUT DATA 0 2 3 4 5 6 7 INPUT DATA VALID SET RI (July, 2002, Version 1.0) 39 AMIC Technology, Inc. A8351601 Series Ordering Information (VCC=5V 10%) Part No. A8351601-40 A8351601L-40 A8351601F-40 RAM 256 Byte 256 Byte 256 Byte FREQ (MHZ) 40 40 40 Package 40L P-DIP 44L PLCC 44L QFP (July, 2002, Version 1.0) 40 AMIC Technology, Inc. A8351601 Series Package Information P-DIP 40L Outline Dimensions unit: inches/mm D 40 21 E1 1 20 E C A2 A A1 Base Plane Seating Plane B B1 e1 0/15 eA L Symbol A A1 A2 B B1 C D E E1 e1 L eA Dimensions in inches Min 0.015 0.150 Nom 0.155 0.018 TYP 0.050 TYP 2.049 0.590 0.542 0.010 2.054 0.600 0.547 0.100 TYP 0.120 0.622 0.130 0.642 0.140 0.662 2.059 0.610 0.552 Max 0.210 0.160 Dimensions in mm Min 0.381 3.810 Nom 3.937 0.457 TYP 1.270 TYP 52.045 14.986 13.767 0.254 52.172 15.240 13.894 2.540 TYP 3.048 15.799 3.302 16.307 3.556 16.815 52.299 15.494 14.021 Max 5.344 4.064 Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. (July, 2002, Version 1.0) 41 AMIC Technology, Inc. A8351601 Series Package Information PLCC 44L Outline Dimension unit: inches/mm HD D 6 1 44 40 39 0.630/0.590 7 17 18 28 29 HE E 0.014/0.0008 C 0.150 REF L A2 e 0.050 REF Seating Plane GD 0.630/0.590 b 0.022/0.016 b1 0.032/0.026 A1 D 0.020 MIN A 0.004 y Dimensions in inches Symbol A D E HD HE L Min 0.648 0.648 0.680 0.680 0.090 0 Nom 0.653 0.653 0.690 0.690 0.100 Max 0.185 0.658 0.658 0.700 0.700 0.110 10 Dimensions in mm Min 16.46 16.46 17.27 17.27 2.29 0 Nom 16.59 16.59 17.53 17.53 2.54 Max 4.70 16.71 16.71 17.78 17.78 2.79 10 Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. (July, 2002, Version 1.0) 42 GE AMIC Technology, Inc. A8351601 Series Package Information QFP 44L Outline Dimensions unit: inches/mm D D1 44 34 See Detail A 1 33 E1 11 23 12 22 E 0.20 min 0 min C 0.25 1.6 DETAIL A Gauge Plane Seating Plane L A2 0.10 D Symbol A A1 A2 b D D1 E E1 L e C Dimensions in inches Min 0.010 0.0748 0.5118 0.3897 0.5118 0.3897 0.0287 0.0021 0 Nom 0.012 0.0787 0.012 TYP 0.5196 0.3937 0.5196 0.3937 0.0346 0.0315 TYP 0.0060 0.0099 7 0.5274 0.3977 0.5275 0.3977 0.0366 Max 0.106 0.014 0.0866 A1 e b A Dimensions in mm Min 0.25 1.9 13.00 9.9 13.00 9.9 0.73 0.1 0 Nom 0.30 2.0 0.3 TYP 13.20 10.00 13.20 10.00 0.88 0.80 TYP 0.15 0.2 7 13.40 10.10 13.40 10.10 0.93 Max 2.7 0.35 2.2 Notes: 1. Dimensions D1 and E1 do not include mold protrusion. 2. Dimension b does not include dambar protrusion. (July, 2002, Version 1.0) 43 AMIC Technology, Inc. |
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